Field of the Invention
The present invention relates to video processing, and in particular, relates to a video decoding system incorporated with a motion compensation hardware acceleration circuit using hardware and software means.
Description of the Related Art
Video compression standards, such as the H.264 standard or the VC-1 standard, have been widely used in commercial video coding/decoding systems. Further, video decoding systems can comprise hardware only or software only systems. Since variable macroblock size motion compensation is adapted in the H.264 and VC-1 standards, it's very difficult to control irregular data flow for decoding a bitstream by hardware only. Accordingly, there is high complexity to design a motion compensation circuit conforming to each size of macroblocks. As for decoding a bitstream by software only, since the size of the macroblocks vary, it's not efficient to decode the bitstream by only using a CPU. If only a CPU is used, the CPU will be burdened when decoding a bitstream with high definition; especially for a CPU operating with a low frequency and low power.